IC BQ24750 skema english
by : lhagus813@gmail.com
IC BQ24750 skema english
Host-controlled Multi-chemistry Battery Charger with Integrated System Power Selector
and AC Over-Power Protection
FEATURES
DETAILED DESCRIPTION
Battery Voltage Regulation
VBATT cell count4V0.5
VVADJ
VVDAC (1)
Battery Current Regulation
ICHARGE
VSRSET
VVDAC
0.10
RSR (2)
Input Adapter Current Regulation
bq24750
SLUS735–DECEMBER 2006
The bq24750 uses a high-accuracy voltage regulator for the charging voltage. The internal default
battery-voltage setting is VBATT = 4.2 V ´ cell count. The regulation voltage is ratiometric with respect to VDAC.
The ratio of VADJ and VDAC provides an extra 12.5% adjustment range on the VBATT regulation voltage. By
limiting the adjustment range to 12.5% of the regulation voltage, the external resistor mismatch error is reduced
from ±1% to ±0.1%. Therefore, an overall voltage accuracy as good as 0.5% is maintained, even while using
1%-mismatched resistors. Ratiometric conversion also allows compatibility with D/As or microcontrollers (mC).
The battery voltage is programmed through VADJ and VDAC using Equation 1.
REGN – Vt = REGN – 0.5 V
The input voltage range of VDAC is between 2.6 V and 3.6 V. VADJ is set between 0 and VDAC. VBATT defaults
to 4.2 V ´ cell count when VADJ is connected to REGN.
CELLS pin is the logic input for selecting cell count. Connect CELLS to charge 2,3, or 4 Li+ cells. When
charging other cell chemistries, use CELLS to select an output voltage range for the charger.
CELLS CELL COUNT
Float 2
AGND 3
VREF 4
The per-cell charge-termination voltage is a function of the battery chemistry. Consult the battery manufacturer
to determine this voltage.
The BAT pin is used to sense the battery voltage for voltage regulation and should be connected as close to the
battery as possible, or directly on the output capacitor. A 0.1-mF ceramic capacitor from BAT to AGND is
recommended to be as close to the BAT pin as possible to decouple high frequency noise.
The SRSET input sets the maximum charge current. Battery current is sensed by resistor RSR connected
between SRP and SRN. The full-scale differential voltage between SRP and SRN is 100 mV. Thus, for a
0.010-W sense resistor, the maximum charging current is 10 A. SRSET is ratiometric with respect to VDAC
using Equation 2:
The input voltage range of SRSET is between 0 and VDAC, up to 3.6 V.
The SRP and SRN pins are used to sense across RSR, with a default value of 10 mW. However, resistors of
other values can also be used. A larger sense-resistor value yields a larger sense voltage, and a higher
regulation accuracy. However, this is at the expense of a higher conduction loss.
The total input current from an AC adapter or other DC sources is a function of the system supply current and
the battery charging current. System current normally fluctuates as portions of the systems are powered up or
down. Without Dynamic Power Management (DPM), the source must be able to supply the maximum system
current and the maximum charger input current simultaneously. By using DPM, the input current regulator
reduces the charging current when the input current exceeds the input current limit set by ACSET. The current
capacity of the AC adapter can be lowered, reducing system cost.
Similar to setting battery regulation current, adapter current is sensed by resistor RAC connected between ACP
and ACN. Its maximum value is set ACSET, which is ratiometric with respect to VDAC, using Equation 3.
IADAPTER
VACSET
VVDAC
0.10
RAC (3)
Adapter Detect and Power Up
Enable and Disable Charging
System Power Selector
bq24750
SLUS735–DECEMBER 2006
The input voltage range of ACSET is between 0 and VDAC, up to 3.6 V.
The ACP and ACN pins are used to sense RAC with a default value of 10 mW. However, resistors of other values
can also be used. A larger sense-resistor value yields a larger sense voltage, and a higher regulation accuracy.
However, this is at the expense of a higher conduction loss.
An external resistor voltage divider attenuates the adapter voltage before it goes to ACDET. The adapter-detect
threshold should typically be programmed to a value greater than the maximum battery voltage, and lower than
the minimum allowed adapter voltage. The ACDET divider should be placed before the ACFET in order to sense
the true adapter input voltage whether the ACFET is on or off. Before the adapter is detected, BATFET stays on
and ACFET turns off.
If PVCC is below 5 V, the device is disabled, and both ACFET and BATFET turn off.
If ACDET is below 0.6 V but PVCC is above 5 V, part of the bias is enabled, including a crude bandgap
reference, ACFET drive and BATFET drive. IADAPT is disabled and pulled down to GND. The total quiescent
current is less than 10 mA.
When ACDET rises above 0.6 V and PVCC is above 5 V, all the bias circuits are enabled and the REGN output
goes to 6 V and VREF goes to 3.3 V. IADAPT becomes valid to proportionally reflect the adapter current.
When ACDET keeps rising and passes 2.4 V, a valid AC adapter is present. 700 ms later, the following occurs:
· ACGOOD goes low through external pull-up resistor to the host digital voltage rail;
· ACFET can turn on and BATFET turns off consequently; (refer to System Power Selector)
· Charging begins if all the conditions are satisfied. (refer to Enable and Disable Charging)
The following conditions must be valid before charge is enabled:
· CHGEN is LOW
· PVCC > UVLO, UVLO = 4 V
· Adapter is detected
· Adapter voltage is higher than BAT + 250 mV
· Adapter is not over voltage (ACOV)
· 700 ms delay is complete after the adapter is detected plus 10 ms ACOC time
· Regulators are at 80% of final voltage
· Thermal Shut (TSHUT) is not valid
· TS is within the temperature qualification window
· VDAC > 2.4 V
The bq24750 automatically switches between connecting the adapter or battery power to the system load. By
default, the battery is connected to the system during power up or when a valid adapter is not present. When the
adapter is detected, the battery is first disconnected from the system, then the adapter is connected. An
automatic break-before-make algorithm prevents shoot-through currents when the selector transistors switch.
The ACDRV signal drives a pair of back-to-back p-channel power MOSFETs (with sources connected together
and to PVCC) connected between the adapter and ACP. The FET connected to the adapter prevents reverse
discharge from the battery to the adapter when it is turned off. The p-channel FET with the drain connected to
the adapter input provides reverse battery discharge protection when off; and also minimizes system power
dissipation, with its low Rdson, compared to a Schottky diode. The other p-channel FET connected to ACP
separates the battery from the adapter, and provides both ACOC current limit and ACOP power limit to the
system. The BATDRV signal controls a p-channel power MOSFET placed between BAT and the system.
When the adapter is not detected, the ACDRV output is pulled to PVCC to turn off the ACFET, disconnecting the
adapter from system. BATDRV stays at ACN – 6 V to connect the battery to system.
At 700 ms after adapter is detected, the system begins to switch from the battery to the adapter. The PVCC
voltage must be 250 mV above BAT to enable the switching. The break-before-make logic turns off both ACFET
and BATFET for 10ms before ACFET turns on. This isolates the battery from shoot-through current or any large
discharging current. The BATDRV output is pulled up to ACN and the ACDRV pin is set to ACN – 6 V by an
internal regulator to turn on the p-channel ACFET, connecting the adapter to the system.
When the adapter is removed, the system waits till PVCC drops back to within 250 mV above BAT to switch
from the adapter back to the battery. The break-before-make logic ensures a 10-ms dead time. The ACDRV
output is pulled up to PVCC and the BATDRV pin is set to ACN – 6 V by an internal regulator to turn on the
p-channel BATFET, connecting the battery to the system.
Asymmetrical gate drive for the ACDRV and BATDRV drivers provides fast turn-off and slow turn-on of the
ACFET and BATFET to help the break-before-make logic and to allow a soft-start at turn-on of either FET. The
soft-start time can be further increased, by putting a capacitor from gate to source of the p-channel power
MOSFETs.
The charger automatically soft-starts the charger regulation current every time the charger is enabled to ensure
there is no overshoot or stress on the output capacitors or the power converter. The soft-start consists of
stepping-up the charger regulation current into 8 evenly divided steps up to the programmed charge current.
Each step lasts approximately 1 ms, for a typical rise time of 8 ms. No external components are needed for this
function.
The synchronous-buck PWM converter uses a fixed-frequency (300 kHz) voltage mode with a feed-forward
control scheme. A Type-III compensation network allows the use of ceramic capacitors at the output of the
converter. The compensation input stage is internally connected between the feedback output (FBO) and the
error-amplifier input (EAI). The feedback compensation stage is connected between the error amplifier input
(EAI) and error amplifier output (EAO). The LC output filter is selected for a nominal resonant frequency of 8
kHz–12.5 kHz.
· CO = C11 + C12
· LO = L1
An internal sawtooth ramp is compared to the internal EAO error-control signal to vary the duty cycle of the
converter. The ramp height is one-fifteenth of the input adapter voltage, making it always directly proportional to
the input adapter voltage. This cancels out any loop-gain variation due to a change in input voltage, and
simplifies the loop compensation. The ramp is offset by 300 mV in order to allow a 0% duty cycle when the EAO
signal is below the ramp. The EAO signal is also allowed to exceed the sawtooth ramp signal in order to operate
with a 100% duty-cycle PWM request. Internal gate-drive logic allows a 99.98% duty-cycle while ensuring that
the N-channel upper device always has enough voltage to stay fully on. If the BTST-to-PH voltage falls below 4
V for more than 3 cycles, the high-side N-channel power MOSFET is turned off and the low-side N-channel
power MOSFET is turned on to pull the PH node down and recharge the BTST capacitor. Then the high-side
driver returns to 100% duty-cycle operation until the (BTST-PH) voltage is detected falling low again due to
leakage current discharging the BTST capacitor below 4 V, and the reset pulse is reissued.
The 300-kHz fixed-frequency oscillator tightly controls the switching frequency under all conditions of input
voltage, battery voltage, charge current, and temperature. This simplifies output-filter design, and keeps it out of
the audible noise region. The charge-current sense resistor RSR should be designed with at least half or more of
the total output capacitance placed before the sense resistor, contacting both sense resistor and the output
inductor; and the other half, or remaining capacitance placed after the sense resistor. The output capacitance
should be divided and placed on both sides of the charge-current sense resistor. A ratio of 50:50 percent gives
the best performance; but the node in which the output inductor and sense resistor connect should have a
minimum of 50% of the total capacitance. This capacitance provides sufficient filtering to remove the switching
noise and give better current-sense accuracy. The Type-III compensation provides phase boost near the
cross-over frequency, giving sufficient phase margin.
The charger operates in non-synchronous mode when the sensed charge current is below the ISYNSET value.
Otherwise, the charger operates in synchronous mode.
During synchronous mode, the low-side N-channel power MOSFET is on when the high-side N-channel power
MOSFET is off. The internal gate-drive logic uses break-before-make switching to prevent shoot-through
currents. During the 30-ns dead time where both FETs are off, the back-diode of the low-side power MOSFET
conducts the inductor current. Having the low-side FET turn-on keeps the power dissipation low, and allows safe
charging at high currents. During synchronous mode, the inductor current always flows, and the device operates
in Continuous Conduction Mode (CCM), creating a fixed two-pole system.
During non-synchronous operation, after the high-side N-channel power MOSFET turns off, and after the
break-before-make dead-time, the low-side N-channel power MOSFET will turn-on for around 80ns, then the
low-side power MOSFET will turn-off and stay off until the beginning of the next cycle, where the high-side
power MOSFET is turned on again. The low-side MOSFET 80-ns on-time is required to ensure that the
bootstrap capacitor is always recharged and able to keep the high-side power MOSFET on during the next
cycle. This is important for battery chargers, where unlike regular dc-dc converters, there is a battery load that
maintains a voltage and can both source and sink current. The 80-ns low-side pulse pulls the PH node
(connection between high and low-side MOSFET) down, allowing the bootstrap capacitor to recharge up to the
REGN LDO value. After the 80 ns, the low-side MOSFET is kept off to prevent negative inductor current from
occurring. The inductor current is blocked by the turned-off low-side MOSFET, and the inductor current becomes
discontinuous. This mode is called Discontinuous Conduction Mode (DCM).
During the DCM mode, the loop response automatically changes and has a single-pole system at which the pole
is proportional to the load current, because the converter does not sink current, and only the load provides a
current sink. This means that at very low currents, the loop response is slower, because there is less sinking
current available to discharge the output voltage. At very low currents during non-synchronous operation, there
may be a small amount of negative inductor current during the 80-ns recharge pulse. The charge should be low
enough to be absorbed by the input capacitance.
Whenever the converter goes into 0% duty-cycle mode, and BTST – PH < 4 V, the 80-ns recharge pulse occurs
on LODRV, the high-side MOSFET does not turn on, and the low-side MOSFET does not turn on (no 80-ns
recharge pulse), and there is no discharge from the battery.
In the bq24750, ISYN is internally set as the charge-current threshold at which the charger changes from
non-synchronous to synchronous operation. The low-side driver turns on for only 80 ns to charge the boost
capacitor. This is important to prevent negative inductor current, which may cause a boost effect in which the
input voltage increases as power is transferred from the battery to the input capacitors. This can lead to
excessive voltage on the PVCC node and potential system damage. This programmable value allows setting the
current threshold for any inductor ripple current, and avoiding negative inductor current. The minimum
synchronous threshold should be set within a range from ½ the inductor ripple current to the full ripple current,
where the inductor ripple current is given by.
to be continued...
